1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more specifically to a device isolation forming method for minimizing a change of a threshold voltage of a MOS transistor at a device isolation region end.
2. Description of Related Art
As a forming method of a device isolation region in a semiconductor device, a selective oxidation such as a LOCOS (local oxidation of silicon) process has been widely used. In this selective oxidation, a lateral oxidation called a "bird's beak" appears remarkably. Therefore, it is necessary to suppress the bird's beak in order to form a fine device formation region. In addition, when the channel width of a MOS transistor is narrowed, it is necessary to prevent a narrow channel effect in which the absolute value of a threshold increases.
Referring to FIG. 10, which is a diagrammatic sectional view of a semiconductor device, a technology for preventing the narrow channel effect in an N-channel MOS transistor (called a "first prior art" hereinafter) adopts a transistor having the following structure. On a device isolation region of a surface of a P-type silicon substrate 401, a field oxide film 405a is formed by the LOCOS process. On a surface of a channel region in a device formation region of the surface of the P-type silicon substrate 401, a gate electrode 408a is formed through a gate oxide film 407a which is formed by a thermal oxidation. In the P-type silicon substrate 401, a P-type punch-through stopper layer 406a is formed. This punch-through stopper layer 406a is isolated from the gate oxide film 407a and is in contact with at least a planar portion of a bottom of the field oxide film 405a. This punch-through stopper layer 406a is formed by ion-implantation after the field oxide film 405a is formed.
In the above mentioned structure, when the field oxide film 405a is formed in the form of suppressing the bird's beak, an electric field concentrating portion 431 occurs at an end of the device isolation region (which is an edge of the field oxide film 405a), with the result that the threshold is apt to lower. In addition, since the punch-through stopper layer 406a is formed by a high energy ion implantation in such a manner that a concentration peak is formed in the proximity of the planar portion of the bottom of the field oxide film 405a, the ion-implanted impurity does not reach (or diffuse) upward sufficiently to influence the P-type impurity concentration in the neighborhood of the surface of the P-type silicon substrate 401. Furthermore, because of segregation of the P-type impurity by a heat treatment for forming the field oxide film 405a and others, a low impurity concentration region 432 is formed in the proximity of the edge of the field oxide film 405a.
Because of the above mentioned causes, in the N-channel MOS transistor there occurs a reverse narrow channel effect in which the narrower the channel width becomes, the lower the threshold becomes. If this reverse narrow channel effect appears, when the threshold of a wide channel width is properly set, in a narrow channel width a sub-threshold leak current flows because of the drop of the threshold. This is an obstruction in reducing the power consumption. In this connection, in order to prevent this problem, if the threshold is set to a high value, the on-current of the transistor lowers. This is an obstacle to speeding-up of the transistor.
On the other hand, in a P-channel MOS transistor, the reverse narrow channel effect does not occur, differently from the N-channel MOS transistor. However, because of segregation of the N-type impurity at the time of forming the field oxide film by the selective oxidation, the N-type impurity concentration becomes extremely high in the proximity of the edge of the field oxide film, with the result that a narrow channel effect becomes remarkable.
A technology for preventing the above mentioned reverse narrow channel effect in the N-channel MOS transistor (called a "second prior art" hereinafter) is disclosed by for example Japanese Patent Application Pre-examination Publication No. JP-A-04-196341. In this disclosed technology, a low impurity concentration region formed in a silicon substrate surface in the proximity of an edge of a field oxide film, is effectively compensated for by forming a P-type impurity concentration adjusting region in the silicon substrate surface in contact with the edge of the field oxide film.
Referring to FIGS. 12A to 12D, which are diagrammatic sectional views for illustrating a manufacturing process of the semiconductor device, the semiconductor device disclosed by JP-A-04-196341 is formed as follows:
Firstly, on a surface of a P-type silicon substrate 401 having the impurity concentration of for example 1.times.10.sup.17 cm.sup.-3, a silicon nitride film, which is an oxidation resistive film, having a thickness of 200 nm is deposited on a low pressure chemical vapor deposition (LPCVD) process. This silicon nitride film is patterned so that a silicon nitride film 402b remains to cover a device formation region of the surface of the P-type silicon substrate 401. By using this silicon nitride film 402b as a mask, a field oxide film 405b having the thickness of 400 nm is formed on a device isolation region of the surface of the P-type silicon substrate 401, by a thermal oxidation at for example 1000.degree. C. (selective oxidation) (FIG. 12A).
Next, a rotary oblique ion implantation of a P-type impurity such as BF.sub.2 is carried out at an angle of 30 degrees to the surface of the P-type silicon substrate 401 under an acceleration voltage of 30 keV and a dose of 2.times.10.sup.13 cm.sup.-2, so that a P-type ion implanted layer (not shown) is formed at the surface of the P-type silicon substrate 401 in contact with the edge of the field oxide film 405b. Furthermore, a heat treatment is carried out to activate the P-type ion implanted layer, so that a P-type impurity concentration adjusting region 424 is formed at the surface of the P-type silicon substrate 401 in contact with the edge of the field oxide film 405b (FIG. 12B).
After the silicon nitride film 402b is removed, a P-type impurity such as boron (B) is ion-implanted onto the whole surface under an acceleration voltage of 150 keV and a dose of 1.times.10.sup.13 cm.sup.-2, so that a second P-type ion implanted layer (not shown) is formed in the P-type silicon substrate 401. The condition for this ion implantation is set to the effect that the concentration peak of the second P-type ion implanted layer is positioned near to the planar portion of the bottom of the field oxide film 405b, but will never be contacted with a bottom of source/drain regions formed of an N.sup.+ diffused layer which will be formed in a later step. Furthermore, a heat treatment is carried out to activate the second P-type ion implanted layer, so that a P-type punch-through stopper layer 406b is formed in the P-type silicon substrate 401. This P-type punch-through stopper layer 406b is in contact with at least the planar portion of the bottom of the field oxide film 405b (FIG. 12C).
Thereafter, a gate oxide film 407b is formed on the device formation region of the surface of the P-type silicon substrate 401, and then, a gate electrode 408b and source/drain regions (not shown) formed of an N.sup.+ diffused layer are formed, so that an N-channel MOS transistor is formed (FIG. 12D).
The above mentioned semiconductor device manufacturing method disclosed by JP-A-04-196341 can be applied for suppressing the narrow channel effect in the P-channel MOS transistor. In this case, an N-type impurity concentration adjusting region is formed in an N-type silicon substrate surface in contact with an edge of an field oxide film, by ion-implanting a P-type impurity (not an N-type impurity) using as a mask the field oxide film and the silicon nitride film which is an oxidation resistive film, so that elevation of the N-type impurity concentration in this portion is effectively canceled.
However, the second prior art has a problem that the reverse narrow channel effect in the N-channel MOS transistor can not be suppressed with a good controllability. Now, this problem will be described with reference to FIGS. 13A and 13B, which are diagrammatic sectional views of a semiconductor device.
Firstly, as shown in FIG. 13A, the P-type impurity concentration adjusting region in the second prior art is formed by ion-implanting to a locally thinned portion using as a mask the silicon nitride film 402ba and the field oxide film 405ba after the field oxide film 405ba is formed. Here, the field oxide film 405ba after the selective oxidation is in the shape that the field oxide film 405ba considerably projects above the P-type silicon substrate 401 at an end of the device formation region in contact with the silicon nitride film 402ba. As a result, the P-type impurity such as BF.sub.2 is ion-implanted into only the surface of the P-type silicon substrate 401 which is not covered by the silicon nitride film 402ba in the neighborhood of the end of the device isolation region. Therefore, an effectively used region is limited to a very narrow region as shown by a dotted line in the drawing. Accordingly, when the film thickness and the shape of the field oxide film 405ba and the implanting angle of the ion implantation vary, it is in some cases that no P-type impurity concentration adjusting region can be formed. In other words, the second prior art has difficulty controlling suppression of reverse narrow channel effect.
JP-A-04-196341 disclosing the above mentioned second prior art also discloses another method for forming the P-type impurity concentration adjusting region. Referring to FIG. 13B, this method is as follows: First, the thickness of the original field oxide film formed by the selective oxidation is thinned (retarded) by an etching, so that a field oxide film 405bb is formed. Thereafter, by using the thinned field oxide film 405bb and the silicon nitride film 402bb as a mask, the P-type impurity such as BF.sub.2 is ion-implanted to the surface of the P-type silicon substrate 401 at an exposed end of the device isolation region, so that the P-type impurity concentration adjusting region is formed in the surface of the P-type silicon substrate 401 at an exposed end of the device isolation region. In this case, the P-type silicon substrate 401 has a shape gouged at the end of the device isolation region, so that a junction depth becomes deep in an end of an N.sup.+ diffused layer which will be formed in a later step for forming the source/drain regions of the N-channel MOS transistor. As a result, the punch-through resistive property between two N.sup.+ diffused layers included in the same MOS transistor is deteriorated, and therefore, it becomes difficult to form a fine device isolation region.
Furthermore, the second prior art also has a problem that the narrow channel effect in the P-channel MOS transistor can not be suppressed with a good controllability. In the case for forming the P-channel MOS transistor, since the N-type impurity concentration adjusting region is formed by the ion implantation of the P-type impurity, there occurs an inconvenience similar to the N-channel MOS transistor.